1. Field of the Invention
The present invention relates to a stack-type capacitor in which a lower electrode is formed of two different metal layers, a semiconductor memory device including the stack-type capacitor, and methods of manufacturing the capacitor and the semiconductor memory device.
2. Description of the Related Art
As the area occupied by a memory cell is scaled down, cell capacitance decreases. A decrease in the cell capacitance is typically a serious obstacle in increasing the integration density of dynamic random access memory (DRAM) devices. In a memory device, a decrease in the cell capacitance not only lowers the ability to read a memory cell and increases a soft error rate, but also hinders the operation of a device at a low voltage. Therefore, a method for increasing cell capacitance is needed for the manufacture of a highly integrated semiconductor memory device.
In order to increase a cell capacitance, cylindrical electrodes are used to increase the area of electrodes.
FIG. 1 illustrates a schematic cross-sectional view of a conventional cylindrical capacitor.
Referring to FIG. 1, an interlayer dielectric (ILD) 11 and an etch stop layer 12 are deposited on a substrate 20, and are patterned to form a contact hole 11a. The contact hole 11a is filled with a conductive plug 13. A lower electrode 14 is formed in a cylindrical shape over the conductive plug 13. A dielectric layer 15 and an upper electrode 16 are sequentially deposited on the lower electrode 14.
The electrodes of the cylindrical capacitor have increased areas, and the cylindrical capacitor has an improved capacitance. The prior art includes a method of manufacturing a cylindrical capacitor in which a hemispherical grain (HSG) is grown on an exposed portion of a cylindrical structure to increase the areas of electrodes.
However, in a highly integrated memory device using this conventional cylindrical capacitor, the inside of a hollow cylindrical structure is so narrow that inner walls may contact each other. To solve this problem, a filled cylindrical stack-type capacitor (hereinafter, referred to as a “stack-type capacitor”) occupying a narrow area is required. Since the sectional area of the stack-type capacitor is smaller than that of a cylindrical capacitor, the integration density of a memory device may be improved.
FIG. 2 illustrates a cross-sectional view of a DRAM cell including a stack-type capacitor having a ruthenium (Ru) electrode.
Referring to FIG. 2, the DRAM cell includes a stack-type capacitor 40 and a switching transistor 30. The transistor 30 includes an n+-type source region 21 and an n+-type drain region 22, which are formed to be spaced apart from each other in a surface of a substrate 20 formed of p-type silicon. A gate insulating layer 31 and a gate electrode 32 are formed on the substrate 20 between the source region 21 and the drain region 22.
The stack-type capacitor 40 is formed on the transistor 30 via an interlayer dielectric (ILD) 33. To form the stack-type capacitor 40, a lower electrode 41, a dielectric layer 43, and an upper electrode 44 are sequentially stacked on the ILD 33. The lower electrode 41 and the upper electrode 44 are formed of ruthenium, and a dielectric material 42, such as Ta2O5, is filled in the lower electrode 41. The source region 21 of the transistor 30 is electrically connected to the lower electrode 41 of the capacitor 40 by a contact hole 33a formed in the ILD 33. The contact hole 33a is filled with a conductive plug 34 formed of polysilicon or tungsten. Also, a conductive barrier layer, e.g., a TiN layer 35, is formed between the conductive plug 34 and the lower electrode 41. The conductive barrier layer 35 is a diffusion barrier layer that prevents mutual diffusion or chemical reactions between the conductive plug 34 and the lower electrode 41. Although it is possible to use a TaN layer or a WN layer, the TiN layer 35 is generally used. The TiN layer 35 isolates the lower electrode 41 from the conductive plug 34, thereby preventing diffusion from the conductive plug 34 into the lower electrode 41 and exposure of the conductive plug 34 to oxygen during deposition. Reference numeral 45 denotes an etch stop layer to be described later.
This stack-type capacitor of FIG. 2, which takes up a smaller area than the conventional cylindrical capacitor of FIG. 1, is more appropriate for a highly integrated memory device.
FIGS. 3A through 3E illustrate cross-sectional views for showing a method of manufacturing a semiconductor memory device including the stack-type capacitor of FIG. 2.
A transistor 30 is formed on a semiconductor substrate 20 by a known semiconductor manufacturing method. Next, a first ILD 33 is formed on the semiconductor substrate 20. The first ILD 33 is selectively etched to form a contact hole 33a, which exposes a source region 21 of the transistor 30. The contact hole 33a is filled with a conductive plug 34 to connect the conductive plug 34 with the source region 21, as shown in FIG. 3A.
Thereafter, an insulating layer 36 is formed on the first ILD 33 to cover the conductive plug 34. The insulating layer 36 is selectively etched to expose the conductive plug 34. A TiN layer 35 is deposited by chemical vapor deposition (CVD) on the insulating layer 36 and then planarized by chemical mechanical polishing (CMP) until the insulating layer 36 and the TiN layer 35 are exposed, as shown in FIG. 3B.
Thereafter, a SiN etch stop layer 45 and a SiO2 second ILD 46 are sequentially stacked on the insulating layer 36 and the TiN layer 35 and then etched by a dry etch process until a portion of the TiN layer 35 is exposed, thereby forming a via hole 46a. An electrode of the capacitor will be formed in the via hole 46a and on the portion of the TiN layer 35 exposed by the via hole 46a. Next, a conductive layer 41, e.g., a Ru layer, is formed by CVD to cover the entire surface of the TiN layer 35 exposed by the via hole 46a, and a Ta2O5 layer 42 is formed thereon (refer to FIG. 3C).
Next, the resultant structure is planarized by CMP until the second ILD 46 is exposed, and the second ILD 46 is etched by a HF wet etch process to form a stack-type lower electrode 41 (refer to FIG. 3D).
Next, a dielectric layer 43 and a Ru upper electrode 44 are sequentially formed on the lower electrode 41, and eventually a stack-type capacitor 40 is completed (refer to FIG. 3E).
However, in this method, when the lower electrode 41 is formed by depositing a Ru layer using CVD, since oxygen is used for a reaction gas, the TiN layer 35 connected to the lower electrode 41 is oxidized and thus volumetrically expands. The volumetric expansion of the TiN layer 35 causes a vacancy between the TiN layer 35 and the Ru lower electrode 41, as shown in the photograph of FIG. 4. Thus, the stack-type capacitor including the Ru lower electrode does not resist and collapses. As shown in FIG. 5, a photograph taken of a storage node shows that a capacitor leans toward and contacts the next capacitor. This degrades electrical properties of the capacitor, thus increasing leakage current.